1. Field of the Invention
The present invention relates to a method for manufacturing contacts on III-V CMOS devices, for example field effect transistors (FETs) such as high electron mobility transistors (HEMTs).
2. Description of the Related Technology
While for semiconductor devices the needs and requirements in terms of communication, in terms of energy and/or in terms of mobility, are increasing, technologies which can handle or deliver the power required for providing higher efficiency and performance to these devices are being developed. Regarding high-power/high-efficiency requirements, performance improvements may be obtained by, for example, the use of new materials for the manufacturing of semiconductor devices. Among those materials, III-nitride materials such as GaN are of growing interest. These materials are direct wide-bandgap semiconductor materials and have initially been brought on the market for their capability to emit blue and white light. In addition to this, because of an electrical breakdown field of more than 10 times larger than that of Si, group III-nitride materials may be used for devices operating in the high-power/high-frequency field, e.g. as replacement material for Si in e.g. Lightly-Doped Drain Metal-Oxide Semiconductor (LDMOS) devices. GaN, which is one of the most popular group III-nitride materials, has shown high-power/high-temperature capabilities which enable its use in applications such as e.g. high-efficiency power conversion.
GaN-based systems may extend system performance beyond the Si intrinsic limits. GaN semiconductor material is characterized by improved electronic and transport properties with respect to Si semiconductor material. Hall mobility of higher than about 2000 cm2/V.s and carrier densities of higher than about 1.2 1013 cm−2 have been reproducibly obtained in AlGaN/GaN heterostructures. Moreover, due to the high bandgap of the GaN semiconductor material, devices with a breakdown voltage of about 1600 V have been reported. However, the cost of this technology may be a drawback. A cost reduction can be achieved with GaN-on-Si technology. AlGaN/GaN high electron mobility transistors (HEMTs) on 150 mm Si substrates have been demonstrated (M. Leys et al., 13th Intl. Conf. on Metal Organic Vapor Phase Epitaxy, Miyazaki, Japan, 22-26 May 2006; IMEC Scientific Report 2006) thereby opening the possibility to combine III-V and Si processes on a same substrate. Thereby source, drain and gate contacts for III-V HEMTs are formed by metal stacks that are patterned by lift-off. The source and drain ohmic contacts are formed by alloying the metal stack at elevated temperatures. A metal which is often used in the metal stack may be Au. In the alloy process, a low barrier height metal compound, i.e. metal compound which forms a contact with low barrier height with the underlying material, is typically formed near the interface and is often combined with a highly doped region near the contact to enhance carrier tunnelling. Gate contacts, on the other hand, are formed of a Schottky metal that is at the bottom combined with an Au-based material to lower the gate resistance. Because of the low patterning yield of lift-off processes and the fast diffusion of Au in semiconductors, current III-V technology is not compatible with state-of-the-art CMOS Si technology.
To achieve a high transconductance and a high saturation current in a semiconductor device, e.g. CMOS device, high quality ohmic contacts with a contact resistance less than 1 Ω.mm are advantageous. A gate with low leakage current, i.e. below about 10−8 mA/mm, low resistivity and good adhesion increases the performance and reliability of the device. For power HEMTs a Schottky gate contact with large barrier height helps to achieve low gate leakage currents, high breakdown voltages and high turn-on voltages. The gate resistance may limit the output power gain and maximum oscillation frequency of the device. The high frequency (HF) performance is better for smaller gate resistances. The gate resistance can be changed by changing the gate structure and the resistance of the gate material. Typical values for the gate resistance are about 50-100 Ω/mm for gate lengths of 1-2 μm.
Scaling down of semiconductor devices has as a consequence scaling down of the gates. Smaller gates lead to higher gate resistance when using the same materials. Therefore high performance of smaller devices depends even more on the quality and resistance of the metallic contacts formed. Furthermore, patterning and reliability of these smaller gates is more difficult.